View STLC307509_4805581.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

march 2009 rev 8 1/36 1 stlc3075 integrated pots interface for home access gateway and wll features monochip slic optimized for wll & voip applications implements all borsht function key features single supply (4.5 v to 12 v) for fly-back configuration single supply (5.5 v to 12 v) for buck-boost configuration built in dc/dc converter controller soft battery reversal with programmable transition time on-hook transmission programmable off-hook detector threshold metering pulse generation and filter integrated ringing integrated ring trip parallel control interface (3.3 v logic level) programmable constant current feed surface mount package integrated thermal protection dual gain value option automatic recognition flyback and buckboost configuration bcdiiis 90v technology -40 c to +85 c operating range description the stlc3075 is a slic device specifically designed for wll (wireless local loop), and isdn terminal adaptors and voip applications. one distinctive characteristic of this device is its ability to operate with a single supply voltage (from +4.5 v to +12 v) and to self generate the negative battery by means of an on-chip dc/dc converter controller that drives an external mos switch. the battery level is properly adjusted depending on the operating mode. a useful characteristic for these applications is the integrated ringing generator. the control interface is parallel with open drain output and 3.3 v logic levels. the metering pulses are generated on-chip starting from two logic signals (0 and 3.3 v): one signal defining the metering pulse frequency, the other signal defining the metering pulse duration. an on-chip circuit then provides the proper shaping and filtering. metering pulse amplitude and shaping (rising and decay time) can be programmed by external components. a dedicated cancellation circuit avoids possible codec input saturation due to metering pulse echo. constant current feed can be set from 20 ma to 40 ma. off-hook detection threshold is programmable from 5 ma to 9 ma. the device, which is developed in bcdiiis technology (90 v process), operates in the extended temperature range and integrates a thermal protection that sets the device in power down when t j exceeds 140 c. table 1. device summary order code package packing e-stlc3075 (1) 1. ecopack? (see section 9 ) lqfp44 tray lqfp44 www.st.com
contents stlc3075 2/36 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 dc/dc converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2.1 power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2.2 high impedance feeding (hi-z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2.3 active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2.4 ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 layout recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2 external components list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.1 test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7 over voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8 typical state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
stlc3075 list of tables 3/36 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 5. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 6. slic operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 7. gain set in active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 8. slic states in active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 9. crest factor values @ 20 and 25hz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 10. external components for buckboost configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 11. vbat values in ring and active modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 12. external components for flyback configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 13. coilcraft type fa2469-al electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 14. coilcraft type fa2470-al electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 15. external components @gain set = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 table 16. external components @gain set = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 table 17. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 18. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
list of figures stlc3075 4/36 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. dc characteristics in hi-z mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. dc characteristics in active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. tip/ring typical transition from direct to reverse polarity . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 6. metering pulse generation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7. tip/ring typical ringing waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 8. application diagram with n-channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 9. application diagram without metering pulse generation with n-channel. . . . . . . . . . . . . . . 23 figure 10. application diagram with p-channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 11. application diagram without metering pulse generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 12. 2w return loss 2wrl = 20log(|zref + zs|/|zref-zs|) = 20log(e/2vs) . . . . . . . . . . . . . . . . 28 figure 13. thl trans hybrid loss thl = 20log|vrx/vtx/ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 14. g24 transmit gain g24 = 20log|2vtx/e| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 15. g42 receive gain g42 = 20log|vi/vrx| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 figure 16. psrrc power supply rejection vpos to 2w port pssrc = 20log|vn/vl| . . . . . . . . . . . . 30 figure 17. l/t longitudinal to transversal conversion l/t = 20log|vcm/vl| . . . . . . . . . . . . . . . . . . . . . 30 figure 18. t/l transversal to longitudinal conversion t/l = 20log|vrx/vcm|. . . . . . . . . . . . . . . . . . . . 30 figure 19. vttx metering pulse level on line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 20. v2wp and w4wp: idle channel sophometric noise at line and tx. v2wp = 20log|vl/0.774l|; v4wp = 20log|vtx/0.774l| . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 21. simplified configuration for indoor over voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 22. standard over voltage protection configuration for k20 compliance . . . . . . . . . . . . . . . . . 32 figure 23. typical state diagram for stlc3075 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 24. lqfp44 (10 x 10 x 1.4 mm) mechanical data and package dimensions . . . . . . . . . . . . . . 34
stlc3075 block diagram 5/36 1 block diagram figure 1. block diagram pd d0 d1 d2 det rttx cac iltf rd iref rlim rth csvr cvcc vpos bgnd tip ring vbat agnd tx rx zac1 zac rs zb cttx1 cttx2 fttx ckttx supervision ttx proc ac proc reference stage line driver crev input logic and decoder output logic volt. vcc vss agnd output reg. status and functions clk rsense gate vf dc/dc conv. dc proc vbat gain setting cz
pin description stlc3075 6/36 2 pin description figure 2. pin connection (top view) 1 2 3 5 6 4 7 8 9 10 17 11 18 19 20 21 22 44 43 42 41 39 40 38 37 36 35 34 28 27 26 24 23 25 33 32 31 29 30 n.c. gain set pd d1 d0 d2 rttx cttx2 cttx1 det ckttx fttx rx zac1 zac zb rs cac tx cz vf n.c. vbat1 crev n.c. tip n.c. n.c. n.c. ring vbat bgnd rlim agnd cvcc rsense gate clk vpos csvr iltf rd iref rth d00tl488 12 13 14 15 16 table 2. pin description n pin function 1 d0 control interface: input bit 0 2 d1 control interface: input bit 1 3 d2 control interface: input bit 2 4 pd power down input. normally connected to cvcc (or to logic level high) 5 gain set control gain interface: 0 level r xgain = 0db t xgain = -12db 1 level r xgain = +6db t xgain = -12db 6, 22, 38, 39, 40, 42 nc not connected 7 det logic interface output of the supervision detector (active low) 8 ckttx metering pulse clock input (12 khz or 16 khz square wave) 9 cttx1 metering burst shap ing external capacitor 10 cttx2 metering burst shaping external capacitor 11 rttx metering pulse cancellation buffer output. ttx filter network should be connected to this point. if not used, should be left open. 12 fttx metering pulse buffer input this signal is sent to the line and used to perform ttx filtering 13 rx 4 wires input port (rx input). a 100 k external resistor must be connected to agnd via the bias input stage. this signal refers to agnd. if connected to single supply codec output it must be dc de coupled with proper capacitor. 14 zac1 rx buffer output (the ac impedance is connected from this node to zac) 15 zac ac impedance synthesis
stlc3075 pin description 7/36 16 rs protection resistors image (the image resi stor is connected from this node to zac) 17 zb balance network for 2 to 4 wire conversion (the balance impedance zb is connected from this node to agnd. za impedance is connected from this node to zac1). 18 cac ac feedback input, ac/dc split capacitor (cac) 19 tx 4 wire output port (tx output). the signal is referred to agnd. if connected to single supply codec input it must be dc decoupled with proper capacitor. 20 cz flyback compensation 21 vf feedback input for dc/dc converter controller 23 clk power switch controller clock (typ. 125 khz). this pin can also be connected to cvcc or agnd. when the clk pin is connected to cvcc an internal auto-oscillation is internally generated and it is used instead of the external clock. when the clk pin is connected to agnd, the gate output is disabled. 24 gate driver for external power mos transistor (p-channel in buckboost configuration, n- channel in flyback configuration). 25 r sense voltage input for current sensing. r sense resistor should be connected close to this pin and v pos pin (buckboost) or gnd (flyback). the pcb layout should minimize the extra resistance introduced by the copper tracks. 26 v pos positive supply input 27 cvcc internal positive voltage supply filter 28 agnd analog ground. must be shorted with bgnd. 29 rlim constant current feed programming pin (v ia rlim). rlim should be connected close to this pin and agnd pin to avoid noise injection. 30 iref internal bias current setting pin. rref should be connected close to this pin and agnd pin to avoid noise injection. 31 rth off-hook threshold programming pin (via rth). rth should be connected close to this pin and agnd pin to avoid noise injection. 32 rd dc feedback and ring trip input. rd should be connected close to this pin and agnd pin to avoid noise injection. 33 iltf transversal line current image output 34 csvr battery supply filter capacitor 35 bgnd battery ground, must be shorted with agnd 36 vbat regulated battery voltage self generated by the device via dc/dc converter. must be shorted to vbat1. 37 ring 2 wire ports; ring wire (ib is the current sunk into this pin) 41 tip 2 wire ports; tip wire (ia is the current sourced from this pin) 43 crev reverse polarity transition time control. a proper capacitor connected between this pin and agnd is setting the reverse polarity transition time. this is the same transition time used to shape the ?trapezoidal ringing? during ringing injection. 44 vbat1 frame connection. must be shorted to vbat table 2. pin description (continued) n pin function
electrical specification stlc3075 8/36 3 electrical specification 3.1 absolute maximum rating 3.2 operating range 3.3 thermal data table 3. absolute maximum ratings symbol parameter value unit v pos positive supply voltage -0.4 to +13 v a/bgnd agnd to bgnd -1 to +1 v v dig pin d0, d1, d2, det , ckttx -0.4 to 5.5 v t j max. junction temperature 150 c v btot (1) 1. vbat is self generated by the on-chip dc/dc c onverter and can be programmed via rf1 and rf2. rf1 and rf2 must be selected in order to fulfil the a.m. limits (see components tables). vbtot=|v pos |+|vbat|. (total voltage applied to the device supply pins). 90 v esd rating human body model 1750 v charged device model 500 v table 4. operating range symbol parameter value unit v pos positive supply voltage 4.5 to +12 v a/bgnd agnd to bgnd -100 to +100 mv v dig pin d0, d1, d2, det , ckttx, pd -0.25 to 5.25 v t op ambient operating temperature range -40 to +85 c v bat (1) 1. vbat is self generated by the on-chip dc/dc c onverter and can be programmed via rf1 and rf2. rf1 and rf2 must be selected in order to fulfil the a.m. limits (see table 10: external components for buckboost configuration ) self generated battery voltage -74 max. v table 5. thermal data symbol parameter value unit r th j-amb thermal resistance junction to ambient typical. 60 c/w
stlc3075 functional description 9/36 4 functional description the stlc3075 is a device specifically developed for wll voip and isdn-ta applications. it is based on a slic core, on purpose optimized for these applications, with the addition of a dc/dc converter controller to meet the wll and isdn-ta design requirements. the slic performs the standard feedin g, signalling and tr ansmission functions. stlc3075 can be set in three different operating modes via the d0, d1, d2 pins of the control logic interface (0 to 3.3 v logic levels). the loop status is carried out on the det pin (active low). the det pin is an open drain output to allow easy interfacing with both 3.3 v and 5 v logic levels. the four possible slic?s operating modes are: ? power down ? high impedance feeding (hi-z) ? active ? ringing ta bl e 6 shows how to set the different slic operating modes. 4.1 dc/dc converter the dc/dc converter controller drives an external power mos transistor n-ch plus transformer (flyback configuration) or p-ch plus inductor (buckboost configuration), in order to generate the negative battery voltage needed for the device operation. the dc/dc converter controller is synchronized with an external clk (125 khz typ.) or with an internal clock generated when the pin clk is connected to cvcc. one r sense in series to pgnd supply (flyback) or to v pos supply (buckboost) allows to fix the maximum allowed input peak current. this feature is implemented in order to avoid overload on v pos supply in case of line transient (ex. ring trip detection). the 110 m typical value guarantees an average current consumption from v pos < 700 ma for buckboost configuration. the 220 m typical value guarantees an average current consumption from v pos < 800 ma for flyback configuration. table 6. slic operating modes pd d0 d1 d2 operating mode 000xpower down 1 0 0 x h.i. feeding (hi-z) 1 0 1 0 active normal polarity 1011active reverse polarity 1 1 1 0 active ttx injection (n.p.) 1 1 1 1 active ttx injection (r.p.) 1 1 0 0/1 ring (d2 bit toggles @ fring)
functional description stlc3075 10/36 the self generated battery voltage is set to a predefined value in on-hook state. the typical value of -50 v can be adjusted via one external resistor (rf1). when ring mode is selected this typical value is increased to -70 v. once the line goes in off-hook condition, the dc/dc converter automatically adjusts the generated battery voltage in order to feed the line with a fixed dc current (programmable via rlim) optimizing the power dissipation. 4.2 operating modes 4.2.1 power down when this mode is selected the slic is switched off and the tip and ring pins are in high impedance. the line detectors are also disabled therefore the off-hook condition cannot be detected. the power down mode can be selected in emergency condition when it is necessary to cut any current delivered to the line. the power down mode is also forced by stlc3075 in case of thermal overload (t j > 140 c). in this case the device goes back to the previous status as soon as the junction temperature decrease under the hysteresis threshold. no ac transmission is possible. 4.2.2 high impedanc e feeding (hi-z) this operating mode is normally selected when the telephone is in on-hook in order to monitor the line status keeping the power consumption at the minimum. the output voltage in on-hook condition is equal to the self generated battery voltage (-50 v typical). when off-hook occurs the det becomes active (low logic level). the off-hook threshold value in hi-z mode is the same as the programmed value in active mode. the dc characteristics in hi-z mode are equal to the self generated battery with 2x(1600 +rp) in series (see figure 3 ), where rp is the external protection resistance. no ac transmission is possible. figure 3. dc characteristics in hi-z mode. vbat il vl vbat (-50v) 2x(r1+rp) slope: 2x(r1+rp) (r1=1600ohm)
stlc3075 functional description 11/36 4.2.3 active dc characteristics & supervision when this mode is selected the stlc3075 provides both dc feeding and ac transmission. the stlc3075 feeds the line with a constant current fixed by rlim (20 ma to 40 ma range). the on-hook voltage is typically 40 v allowing on-hook transmission; the self generated vbat is -50 v typical. if the loop resistance is very high and the line current cannot reach the programmed constant current feed value, the stlc3075 behaves like a 40 v voltage source with a series impedance equal to the protection resistors 2xrp (typ. 2x50 ). figure 4. shows the typical dc characteristics in active mode. the line status (on/off hook) is monitored by the slic?s supervision circuit. the off-hook threshold can be programmed via the external resistor rth in the range from 5ma to 9ma. independently on the programmed constant current value, the tip and ring buffers have a current source capability limited to 80ma typical. figure 4. dc characteristics in active mode moreover the power available at vbat is controlled by the dc/dc converter that limits the peak current drawn from the v pos supply. the maximum allowed current peak is set by r sense resistor. il ilim vl vbat (-50v) 10v 2rp (20 to 40ma)
functional description stlc3075 12/36 ac characteristics the slic provides the standard slic transmission functions. once in active mode the slic can operate with two different tx, rx gains set by the gain set control bit (see ta bl e 7 below). input impedance synthesis : can be real or complex and is set by a scaled (x 50 or x 25) external zac impedance transmit and receive : the ac signal present on the 2w port (tip and ring pins) is transferred to the tx output with a -6 db or -12 db gain and from the rx input to the 2w port with a 0 db or +6 db gain 2 to 4 wires conversion : the balance impedance can be real or complex, the proper cancellation is obtained by means of two external impedances za and zb once in active mode (d1=1) the slic can operate in different states setting properly d0 and d2 control bits (see also ta b l e 8 ). polarity reversal the d2 bit controls the line polarity, the transition between the two polarities is performed in a ?soft? way. this means that the tip and ring wires exchange their polarities following a ramp transition (see figure 5 ). the transition time is controlled by an external capacitor crev. this capacitor also sets the shape of the ringing trapezoidal waveform. when the control pins set the battery reversal, the line polarity is reversed with a proper transition time set via an external capacitor (crev). figure 5. tip/ring typical transition from direct to reverse polarity table 7. gain set in active mode gain set 4 to 2 wires gain 2 to 4 wires gain impedance synthesis scale factor 0 0 db -6 db x 50 1 +6 db -12 db x 25 table 8. slic states in active mode d0 d1 d2 operating mode 0 1 0 active normal polarity 0 1 1 active reverse polarity 1 1 0 active ttx injection (normal polarity.) 1 1 1 active ttx injection (reverse polarity.) gnd tip ring dv/dt set by crev 4v typ. 40v typ on-hook
stlc3075 functional description 13/36 metering pulse injection (ttx) the metering pulses circuit consists of a burst shaping generator that generates a square shaped wave and a low pass filter to reduce the harmonic distortion of the output signal. the metering pulse is obtained from two logic signals: ckttx : is a square wave at the ttx frequency (12 or 16khz) that must be permanently applied to the ckttx pin or at least for all the duration of the ttx pulse (including rising and decay phases). d0 : enables the ttx generation circuit and defines the ttx pulse duration. these two signals are processed by a dedicated circuitry integrated on chip that generates the metering pulse as an amplitude modulated shaped square wave (sqttx) (see figure 6 ). both the amplitude and the envelope of the square wave (sqttx) can be programmed by means of external components. in particular the amplitude is set by the two rlv resistors while the shaping is set by the cs capacitor. figure 6. metering pulse generation circuit the waveform so generated is then filtered and injected on the line. the low pass filter is obtained by using the integrated buffer op1 connected between pin fttx (op1 non inverting input) and rttx (op1 output) (see figure 6 ) and by implementing a ?sallen and key? configuration. depending on the external components count it is possible to build an optimized application depending on the distortion level required. in particular harmonic distortion levels equal to 13 %, 6 % and 3 % can be obtained respectively with first, second and third order filters (see figure 6 ). the circuit showed in the ?application diagram? is related to the simp le first order filter. once the shaped and filtered signal is obtained at rttx buffer output it is injected on the tip/ring pins with a +6 db gain or +12 db gain. it should be noted that this is the nominal condition obtained in presence of ideal ttx echo cancellation (obtained via proper setting of rttx and cttx). in addition the effective level obtained on the line will depend on the line impedance and the protection resistors value. in typical applications (ttx line impedance =200 , rp = 50 , cttx1 cttx2 cs rlv rlv sqttx burst d0 ckttx shaping generator square wave pulse metering sinusoidal wave pulse metering rttx fttx low pass filter - + op1 cfl r1 r2 c2 c1 required external components vs. filter order. order cfl r1 c1 r2 c2 thd 1x 13% 2 xxxx6% 3 xxxxx3%
functional description stlc3075 14/36 and ideal ttx echo cancellation), the metering pulse level on the line equals 1.33 or 2.66 times the level applied to the rttx pin. as already mentioned the metering pulse echo cancellation is obtained by means of two external components (rttx and cttx) that should match the line impedance at the ttx frequency. this simple network has a double effect: it synthesizes a low output impedance at the tip/ring pins at the ttx frequency it cuts the eventual ttx echo that would have been transferred from the line to the tx output 4.2.4 ringing when this mode is selected, the stlc3075 self generates a higher negative battery (-70 v typ.) in order to allow a balanced ringing signal of typically 65 v peak. in this condition both the dc and ac feedback loops are disabled and the slic line drivers operate as voltage buffers. the ring waveform is obtained by toggling the d2 control bit at the desired ring frequency. this bit in fact cont rols the line polarity (0=direct; 1= reverse). as in the active mode the line voltage transition is performed with a ramp transition, obtaining in this way a trapezoidal balanced ring waveform (see figure 7 ). the shaping is defined by the crev external capacitor. figure 7. tip/ring typical ringing waveform selecting the proper capacitor value it is possible to get different crest factor values. the following table shows the crest factor values obtained with a 20 hz and 25 hz ring frequency and with 1ren. these value are valid either with european or usa specification: the ring trip detection is performed by sensing the variation of the ac line impedance from on-hook (relatively high) to off-hook (low). this particular ring trip method allows to operate without dc offset superimposed on the ring signal and therefore obtaining the maximum possible ring level on the load starting from a given negative battery. it should be noted that such a method is optimized for operation on short loop applications and may not operate properly in the case of long loop applications (> 500 ). table 9. crest factor values @ 20 and 25hz crev crest factor @20hz crest factor @25hz 22 nf 1.2 1.26 27 nf 1.25 1.32 33 nf 1.33 not significant (1) 1. distortion already less than 10% gnd tip ring dv/dt set by crev 2.5v typ. 65v typ. vbat 2.5v typ.
stlc3075 functional description 15/36 once the ring trip is detected, the det output is activated (logic level low). at this point the card controller or a simple logic circuit stops the d2 toggling in order to effectively disconnect the ring signal and then set the stlc3075 in the proper operating mode (normally active). ring level in presence of more telephones in parallel as already mentioned in the previous section, the maximum current that can be drawn from the v pos supply is controlled and limited via the external r sense . this also limits the power available at the self generated negative battery. if for any reason the ringer load is too low, the self generated battery drops in order to keep the power consumption to the fixed limit and consequently the ring voltage level is also reduced. in the typical buckboost configuration with r sense = 110 m the peak current from v pos is limited to around 900 mapk, which correspond to an average current of 700 ma max. in this condition the stlc3075 can drive up to 3ren with a ring frequency fr=25 hz (1ren = 1800 + 1.0 f, european standard). in order to drive up to 5ren (1ren= 6930 + 8 f, us standard) it is necessary to modify the external components as follows: crev = 15nf; rd = 2.2 k ; r sense = 100 m . in flyback configuration the value of r sense = 220 m guarantees to match both european and usa standards. in order to drive 5ren (us standard) it is necessary to modify the external component: r d = 2.2 k .
application information stlc3075 16/36 5 application information 5.1 layout recommendation a properly designed pcb layout is a basic issue to guarantee a correct behavior and good noise performance. particular care must be taken on the ground connection. using the configurations shown on figure 10 and figure 11 permits to avoid possible problems. the ground of the power supply (v pos ) has to be connected to the center of the star, named as system-gnd. this point should show a resistance as low as possible, that means it should be a ground plane. in particular to avoid noise problems the layout should prevent any coupling between the dc/dc converter components and analog pins that are referred to agnd (ex: rd, iref, rth, rlim, vf). as a first recommendation the components cv, l, t1, d1, cv pos , r sense should be kept as close as possible to each other and isolated from the other components. additional improvements can be obtained ? by decoupling the center of the star from the analog ground of stlc3075 using small chokes ? by adding a capacitor in the range of 100 nf between v pos and agnd in order to filter the switch frequency on v pos 5.2 external components list in order to properly define the external components value the following system parameters have to be defined: the ac input impedance shown by the slic at the line terminals zs to which the return loss measurement is referred. it can be real (typ. 600 ) or complex. the ac balance impedance, it is the equivalent impedance of the line ?zl? used for evaluation of the trans-hybrid loss performances (2/4 wire conversion). it is usually a complex impedance. the value of the two protection resistors rp in series with the line termination. the line impedance at the ttx frequency zlttx the metering pulse level amplitude measured at line termination v lottx . in case of low order filtering, v lottx represents the amplitude (vrms) of the fundamental frequency component (typ. 12 or 16 khz) the pulse metering envelope rise and decay time constant the slope of the ringing waveform v tr / t the value of the constant current limit current ?ilim? the value of the off-hook current threshold i th the value of the ring trip rectified average threshold current i rth the value of the required self generated negative battery v batr in ring mode (max value is 70v). this value can be obtained from the desired ring peak level + 5v. the value of the maximum current peak drawn from v pos ?ipk?.
stlc3075 application information 17/36 table 10. external components for buckboost configuration name function formula typ. value rrx rx input bias resistor 100 k 5% rref bias setting current rref = 1.3/ibias ibias = 50 a 26 k 1% csvr negative battery filter csvr = 1/(2 ? fp ? 1.8 m ) fp = 50 hz 1.5 nf 10% 100 v rd ring trip threshold setting resistor rd = 100/i rth 2k < rd < 5 k 4.12 k 1%@ irth = 24 ma cac ac/dc split capacitance 22 f 20% 15 v @ rd = 4.12 k rp line protection resistor rp > 30 50 1% rlim current limiting programming rlim = 1300/ilim 32.5 k < rlim < 65 k 52.3 k 1% @ ilim = 25 ma rth off-hook threshold programming (active mode) rth = 290/i th 27 k < rth < 52 k 32.4 k 1% @ i th = 9 ma crev reverse polarity transition time programming crev = ((1/3750) t/ v tr ) 22 nf 10% 10v @ 12 v/ms rdd pull up resistors 100 k cvcc internally supply filter capacitor 100 nf 20% 10 v cv pos positive supply filter capacitor with low impedance for switch mode power supply 100 f (1) cv battery supply filter capacitor with low impedance for switch mode power supply 100 f 20% 100v (2) cvb high frequency noise filter 470 nf 20% 100 v crd (3) high frequency noise filter 100 nf 10% 15 v q1 dc/dc converter switch p ch. mos transistor rds(on) 1.2 , vds = -100 v total gate charge= 20 nc max. with vgs=4.5 v and vds=1 v id>500 ma possible choices: irf9510 or irf9520 or irf9120 or equivalent d1 dc/dc converter series diode v r > 100 v, t rr 50 ns smbyw01-200 or equivalent r sense dc/dc converter peak current limiting r sense = 100mv/i pk 110 m @ i pk = 900 ma rf1 negative battery programming level 250k < rf1 < 300k (4) 300 k 1% @ v batr = -70 v rf2 negative battery programming level 9.1 k 1% l dc/dc converter inductor dc resistance 0.1 (5) l=100 h sumida cdrh125 or equivalent
application information stlc3075 18/36 1. cv pos should be defined depending on the power supply cu rrent capability and maxi mum allowable ripple 2. for low ripple application use 2x47m f in parallel. 3. can be saved if proper pcb layout avoid noise coupling on rd pi n (high impedance input). 4. rf1 sets the self generated battery voltage in ring and active(il=0) mode as shown in table 11 . vbatr should be defined considering the ring peak level required (vringpeak=vbatr - 6 v typ.). this relation is valid providing that the v pos power supply current capability and the r sense programming allow to source all the current requested by the particular ringer load configuration 5. for high efficiency in hi-z mode coil resistance @125khz must be < 3 . table 11. vbat values in ring and active modes 267k 280k 294k 300k vbat (active) -46v -48v -49v -50v vbatr (ring) -62v -65v -68v -70v
stlc3075 application information 19/36 table 12. external components for flyback configuration name function formula typ. value rrx rx input bias resistor 100 k 5% rref bias setting current rref = 1.3/ibias; ibias = 50 a 26 k 1% csvr negative battery filter csvr = 1/(2 ? fp ? 1.8 m ) fp = 50 hz 1.5 nf 10 % 100 v rd ring trip threshold setting resistor rd = 100/i rth 2k < rd < 5 k 4.12 k 1% @ irth = 24 ma cac ac/dc split capacitance 22 f 20% 15 v @ rd = 4.12 k rp line protection resistor rp > 30 50 1% rlim current limiting programming rlim = 1300/ilim 32.5 k < rlim < 65 k 52.3 k 1% @ ilim = 25 ma rth off-hook threshold programming (active mode) rth = 290/i th 27 k < rth < 52 k 32.4 k 1% @ i th = 9 ma crev reverse polarity transition time programming crev = ((1/3750) t/ v tr ) 22 nf 10% 10 v @ 12 v/ms rdd pull up resistors 100 k cvcc internally supply filter capacitor 100 nf 20 % 10 v cv pos positive supply filter capacitor with low impedance for switch mode power supply 100 f (1) cv battery supply filter capacitor with low impedance for switch mode power supply 100 f 20 % 100 v (2) cvb high frequency noise filter 470 nf 20% 100 v crd (3) high frequency noise filter 100 nf 10% 15 v cz flyback compensation capacitor 2.2 nf, 20 % csf sense filter capacitor 120 pf, 20 % rsf sense filter resistor 1 k r sense dc/dc converter peak current limiting r sense = 375 mv/i pk 220 m @ i pk = 1.7 a q1 dc/dc converter switch n channel mos transistor rds(on) 0.05 , vdss = 30 v vdg=30 v, id = 6.5 a low threshold drive stn4nf03l or equivalent d1 dc/dc converter series diode v r > 350 v, t rr 80 ns smbytw01-400 or equivalent t1 dc/dc converter transformer flyback transformer 4w, turns ratio 1:16 for v pos range from 4.5 v to 8.5 v tyco coev magnetics mgpwg-00007 or coilcraft fa2469-al (4)
application information stlc3075 20/36 t1 dc/dc converter transformer flyback transformer 4w, turns ratio 1:8 for v pos range from 8.5 v to 12 v tyco coev magnetics mgpwg-00008 or coilcraft fa2470-al (5) rf1 negative battery programming level 250 k stlc3075 application information 21/36 table 15. external components @gain set = 0 name function formula typ. value rs protection resistance image rs = 50 ? (2rp) 5 k @ rp = 50 zac two wire ac impedance zac = 50 ? (zs - 2rp) 25 k 1% @ zs = 600 za (1) slic impedance balancing network za = 50 ? zs 30 k 1% @ zs = 600 zb (1) line impedance balancing network zb = 50 ? zl 30 k 1% @ zl = 600 ccomp ac feedback loop compensation fo = 250 khz ccomp = 1/(2 ? fo ? 100 ? (rp)) 120 pf 10 % 10 v @ rp = 50 ch trans-hybrid loss frequency compensation ch = ccomp 120 pf 10 % 10 v rttx (2) pulse metering cancellation resistor rttx = 50re (zlttx+2rp) 15 k @ zlttx = 200 real cttx (2) pulse metering cancellation capacitor cttx = 1/{50 ? 2 ? fttx [-lm(zlttx)]} 100 nf 10% 10 v (3) @ zlttx = 200 real rlv pulse metering level resistor rlv = 63.310 3 v lottx = (|zlttx + 2rp|/|zlttx|) 16.2 k @ v lottx = 170 mvrms cs pulse metering shaping capacitor cs = /(2 ? rlv) 100 nf 10 % 10 v @ = 3.2 ms, rlv = 16.2 k cfl pulse metering filter capacitor cfl = 2/(2 ? fttx ? rlv) 1.5 nf 10 % 10 v @fttx = 12 khz rlv = 16.2 k 1. in case zs=zl, za and zb can be replaced by two resistors of same value: ra=rb=|zs|. 2. defining zttx as the impedance of rttx in series with cttx , rttx and cttx can also be calculated from the following formula: zttx=50*(zlttx+2rp). 3. in this case cttx is just operating as a dc decoupling capacitor (fp=100 hz).
application information stlc3075 22/36 table 16. external components @gain set = 1 name function formula typ. value rs protection resistance image rs = 50 ? (2rp) 5 k @ rp = 50 zac two wire ac impedance zac = 50 ? (zs - 2rp) 25 k 1% @ zs = 600 za (1) slic impedance balancing network za = 50 ? zs 30 k 1% @ zs = 600 zb (1) line impedance balancing network zb = 50 ? zl 30 k 1% @ zl = 600 ccomp ac feedback loop compensation fo = 250 khz ccomp = 1/(2 ? fo ? 100 ? (rp)) 120 pf 10 % 10 v @ rp = 50 ch trans-hybrid loss frequency compensation ch = ccomp 120 pf 10 % 10 v rttx (2) pulse metering cancellation resistor rttx = 50re (zlttx+2rp) 15 k @ zlttx = 200 real cttx (2) pulse metering cancellation capacitor cttx = 1/{50 ? 2 ? fttx [-lm(zlttx)]} 100 nf 10 % 10 v (3) @ zlttx = 200 real rlv pulse metering level resistor rlv = 63.310 3 v lottx = (|zlttx + 2rp|/|zlttx|) 16.2 k @ v lottx = 170 mvrms cs pulse metering shaping capacitor cs = /(2 ? rlv) 100 nf 10 % 10 v @ = 3.2 ms, rlv = 16.2 k cfl pulse metering filter capacitor cfl = 2/(2 ? fttx ? rlv) 1.5 nf 10 % 10 v @fttx = 12 khz rlv = 16.2 k 1. in case zs=zl, za and zb can be replaced by two resistors of same value: ra=rb=|zs|. 2. defining zttx as the impedance of rttx in series with cttx , rttx and cttx can also be calculated from the following formula: zttx=50*(zlttx+2rp). 3. in this case cttx is just operating as a dc decoupling capacitor (fp=100 hz).
stlc3075 application information 23/36 figure 8. application diagram with n-channel figure 9. application diagram without me tering pulse generation with n-channel zac rs za zb ccomp tx zac1 zac zb gain set tx control interface d0 d1 d2 bgnd cvcc cac cac iref rref gate vbat q1 r sense t1 rf1 clk crev crev d04tl625a csvr stlc3075 d0 d1 d2 det det iltf rlim rlim rth rth csvr rp tip agnd vpos vpos ch d1 rx rx rs cttx2 rttx cs cfl rlv rlv ttx clock cttx cvcc rsense rf2 cv vf clk rp ring tip ring cvpos rdd rd rd ckttx cttx1 fttx rttx system gnd agnd bgnd suggested ground lay-out vdd cvb csf rsf crd pgnd n-ch cz cz pd pd rrx zac r s za zb ccomp tx zac1 zac zb tx control interface d0 d1 d2 bgnd cvcc cac cac iref rref r s en s e vbat rf1 clk crev crev d04tl626 c s vr s tlc 3 075 d0 d1 d2 det det iltf rlim rlim rth rth c s vr rp tip agnd vpo s vpo s ch rx rx r s 10re s 11re s cvcc gate rf2 vf clk rp ring tip ring cvpo s rdd rd rd 8 re s 9re s 12re s s y s tem gnd agnd bgnd s ugge s ted ground lay-out vdd cvb c s f r s f crd pgnd gain s et q1 r s en s e t1 d1 cv n-ch cz cz pd pd rrx
application information stlc3075 24/36 figure 10. application diagram with p-channel figure 11. application diagram wi thout metering pulse generation (*) buckboost configuration. zac rs za zb ccomp tx zac1 zac zb tx control interface d0 d1 d2 bgnd cvcc cac cac iref rref gate vbat p-ch q1 rf1 clk crev crev d01tl493b csvr stlc3075 d0 d1 d2 det det iltf rlim rlim rth rth csvr rp tip agnd vpos vpos ch rsense d1 rx rx rs cttx2 rttx cs cfl rlv rlv ttx clock cttx cvcc rsense rf2 cv vf l clk rp ring tip ring cvpos rdd rd rd ckttx cttx1 fttx rttx system gnd agnd bgnd suggested ground lay-out vdd cvb crd pgnd gain set pd pd rrx zac rs za zb ccomp tx zac1 zac zb tx control interface d0 d1 d2 bgnd cvcc cac cac iref rref gate vbat p-ch q1 rf1 clk crev crev d01tl494b csvr stlc3075 d0 d1 d2 det det iltf rlim rlim rth rth csvr rp tip agnd vpos vpos ch rsense d1 rx rx rs cttx2 rttx cvcc rsense rf2 cv vf l clk rp ring tip ring cvpos rdd rd rd ckttx cttx1 fttx system gnd agnd bgnd suggested ground lay-out vdd cvb crd pgnd gain set pd pd rrx
stlc3075 electrical characteristics 25/36 6 electrical characteristics test conditions: v pos = 6.0v, agnd = bgnd, normal polarity, t amb = 25c. external components as listed in the ?typical values? column of the above external components tables. note: testing of all parameters is performed at 25c. characterization as well as design rules used allow correlation of tested performances at other temperatures. all parameters listed here are met in the operating range of: -40 to +85c. table 17. electrical characteristics symbol parameter test cond ition min. typ. max. unit dc characteristics v lohi line voltage il = 0 hi-z (high impedance feeding) t amb = 0c to 85 c 44 50 v v lohi line voltage il = 0 hi-z (high impedance feeding) t amb = -40 c to 85 c 42 48 v v loa line voltage il = 0, active mode, t amb = 0 c to 85 c 33 40 v v loa line voltage il = 0, active mode, t amb = -40 c to 85 c 31 37 v ilim lim. current programming range active mode 20 40 ma ilima lim. current accuracy active mode rel. to programmed value 20 ma to 40ma -10 10 % rfeed hi feeding resistance hi-z (high impedance feeding) 2.4 3.6 k ac characteristics l/t long. to transv. (see appendix for test circuit) rp = 50 , 1% tolerance active n. p., r l = 600 (*) f = 300 to 3400 hz 50 58 db t/l transv. to long. (see appendix for test circuit) rp = 50 , 1 % tolerance active n. p., r l = 600 (*) f = 300 to 3400 hz 40 45 db t/l transv. to long. (see appendix for test circuit) rp = 50 , 1% tolerance active n. p., r l = 600 (*) f = 1 khz 48 53 db 2wrl 2w return loss 300 to 3400 hz active n. p., r l = 600 (*) 22 26 db
electrical characteristics stlc3075 26/36 thl trans-hybrid loss 300 to 3400 hz 20log|vrx/vtx| active n. p., r l = 600 (*) 30 db ovl 2w overload level at line terminals on ref. imped. active n. p., r l = 600 (*) 3.2 dbm txoff tx output offset active n. p., r l = 600 (*) -250 250 mv g24 transmit gain abs. 0 dbm @ 1020 hz active n. p., r l = 600 (*) -6.4 -5.6 db g42 receive gain abs. 0 dbm @ 1020 hz active n. p., r l = 600 (*) -0.4 0.4 db g24f tx gain variation vs. frequency rel. 1020 hz; 0 dbm 300 to 3400 hz active n. p., r l = 600 (*) -0.12 0.12 db g24f rx gain variation vs. freq. rel. 1020 hz; 0dbm 300 to 3400 hz active n. p., r l = 600 (*) -0.12 0.12 db v2wp idle channel noise at line 0db gain set psophometric filtered active n. p., r l = 600 (*) t amb = 0 to +85 c -73 -68 dbmp v2wp idle channel noise at line 0db gain set psophometric filtered active n. p., r l = 600 (*) t amb = -40 to +85 c -68 dbmp v4wp idle channel noise at line 0db gain set psophometric filtered active n. p., r l = 600 (*) t amb = 0 to +85 c -75 -70 dbmp v4wp idle channel noise at line 0db gain set psophometric filtered active n. p., r l = 600 (*) t amb = -40 to +85 c -75 dbmp thd total harmonic distortion active n. p., r l = 600 (*) -44 db vttx metering pulse level on line active - ttx; gain set = 1 zl = 200 fttx = 12 khz 260 340 mvr ms clkfreq clk operating range -10% 125 10% khz (*) r l : line resistance ring vring line voltage ring d2 toggling @ fr = 25 hz load = 3ren crest factor = 1.25 1ren = 1800 + 1.0 f t amb = 0 to +85 c 45 49 vrms table 17. electrical characteristics (continued) symbol parameter test cond ition min. typ. max. unit
stlc3075 electrical characteristics 27/36 vring line voltage ring d2 toggling @ fr = 25 hz load = 3ren crest factor = 1.25 1ren = 1800 + 1.0 f t amb = -40 to +85 c 44 48 vrms detectors iofftha off/hook current threshold active mode, rth = 32.4 k 1% (prog. ith = 9 ma) 10.5 ma roftha off/hook loop resistance threshold active mode, rth = 32.4 k 1% (prog. ith = 9 ma) 3.4 k iontha on/hook current threshold active mode, rth = 32.4 k 1% (prog. ith = 9 ma) 6ma rontha on/hook loop resistance threshold active mode, rth = 32.4 k 1% (prog. ith = 9 ma) 8k ioffthi off/hook current threshold hi z mode, rth = 32.4 k 1% (prog. ith = 9 ma) 10.5 ma roffthi off/hook loop resistance threshold hi z mode, rth = 32.4 k 1% (prog. ith = 9 ma) 800 ionthi on/hook current threshold hi z mode, rth = 32.4 k 1% (prog. ith = 9 ma) 6ma ronthi on/hook loop resistance threshold hi z mode, rth = 32.4 k 1% (prog. ith = 9 ma) 8k irt ring trip detector threshold range ring 20 50 ma irta ring trip detector threshold accuracy ring -15 15 % trtd ring trip detection time ring 60 ms td dialling distortion active mode -1 1 ms rlrt (1) loop resistance 500 thal tj for th. alarm activation 160 c (1) rlrt = maximum loop resistance (incl. telephone) for correc t ring trip detection. digital interface inputs: d0, d1, d2, pd, clk outputs: det vih in put high voltage 2 v vil input low voltage 0.8 v iih input high current -10 10 a iil input low current -10 10 a vol output low voltage iol = 1ma 0.45 v table 17. electrical characteristics (continued) symbol parameter test cond ition min. typ. max. unit
electrical characteristics stlc3075 28/36 6.1 test circuits referring to the application diagram as shown on figure 10: application diagram with p- channel and using the typical values from table 10: external components for buckboost configuration and table 15: external components @gain set = 0 find below the proper configuration for each measurement. all measurements requiring dc current termination should be performed using ?wandel & glittering? dc loop holding circuit gh-1? or equivalent. figure 12. 2w return loss 2wrl = 20log(|zref + zs|/|zref-zs|) = 20log(e/2vs) psrr and power consumption pserrc power supply rejection v pos to 2w port vripple = 100 mvrms 50 to 4000 hz 26 36 db ivpos v pos supply current @ ii = 0 hi-z on-hook active on-hook ring (line open) 13 50 55 25 80 90 ma ma ma ipk (1) peak current limiting accuracy ring off-hook r sense = 110 m -20% 900 +20% mapk 1. buck-boost configuration table 17. electrical characteristics (continued) symbol parameter test cond ition min. typ. max. unit zref w&g gh1 tip tx s tlc 3 075 a pplic a tion circ u it 600ohm 1kohm 1kohm v s ring rx e 100 f 100ma dc m a c zin = 100k 200 to 6khz 100 f
stlc3075 electrical characteristics 29/36 figure 13. thl trans hybrid loss thl = 20log|vrx/vtx / figure 14. g24 transmit gain g24 = 20log|2vtx/e| figure 15. g42 receive gain g42 = 20log|vi/vrx | w&g gh1 tip tx s tlc 3 075 a pplic a tion circ u it 600ohm ring rx 100 f 100ma dc m a c zin = 100k 200 to 6khz 100 f vrx vtx tip ring rx tx stlc3075 application circuit w&g gh1 e vtx 100 f 100 f 100ma dc max zin = 100k 200 to 6khz 600ohm tip ring rx tx stlc3075 application circuit w&g gh1 vrx vl 100 f 100 f 100ma dc max zin = 100k 200 to 6khz 600ohm
electrical characteristics stlc3075 30/36 figure 16. psrrc power supply rejection v pos to 2w port pssrc = 20log|vn/vl | figure 17. l/t longitudinal to tran sversal conversion l/t = 20log|vcm/vl| figure 18. t/l transversal to longi tudinal conversion t/l = 20log|vrx/vcm | tip ring rx tx stlc3075 application circuit w&g gh1 vl 100 f 100 f 100ma dc max zin = 100k 200 to 6khz 600ohm vn vpos ~ tip ring rx tx stlc3075 application circuit w&g gh1 vcm vl 100 f 100 f 100ma dc max zin = 100k 200 to 6khz 300ohm 100 f 300ohm 100 f impedance matching better than 0.1% 600ohm tip ring rx tx stlc3075 application circuit vcm w&g gh1 100 f 100 f 100ma dc max zin = 100k 200 to 6khz 300ohm 100 f 300ohm 100 f impedance matching better than 0.1% vrx
stlc3075 electrical characteristics 31/36 figure 19. vttx metering pulse level on line figure 20. v2wp and w4wp: idle channel sophometric noise at line and tx. v2wp = 20log|vl/0.774l|; v4wp = 20log|vtx/0.774l | tip ring rx tx stlc3075 application circuit fttx (12 or 16khz) vlttx 200ohm ckttx tip ring rx tx stlc3075 application circuit w&g gh1 vl psophometric filtered 100 f 100 f 100ma dc max zin = 100k 200 to 6khz 600ohm vtx psophometric filtered
over voltage protection stlc3075 32/36 7 over voltage protection figure 21. simplified configuration for indoor over voltage protection figure 22. standard over voltage protection configuration for k20 compliance tip ring bgnd vbat rp1 rp2 rp1 rp2 2 x sm6t39a stlc3075 tip ring rp1 = 30ohm: rp2 =fuse or ptc > 18ohm stpr120a stpr120a tip bgnd vbat rp1 rp2 rp1 = 30ohm: rp2 =fuse or ptc > 18ohm 2 x sm6t39a stlc3075 tip ring rp1 rp2 ring lcp1521s
stlc3075 typical state diagram 33/36 8 typical state diagram figure 23. typical state diagram for stlc3075 operation tj>tth pd=0, d0=d1=0 pd=1, d0=d1=0 power down hi-z feeding off hook detection active off hook on hook detection for t>tref active on hook ringing ring burst d0=1, d1=0, d2=0/1 ring trip detection normally used for on hook transmission ring pause d0=0, d1=1, d2=0 ring burst off hook detection d0=0, d1=1, d2=0 on hook condition note: all state transitions are under the microprocessor control.
package information stlc3075 34/36 9 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 24. lqfp44 (10 x 10 x 1.4 mm) mechanical data and package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.015 0.018 c 0.09 0.20 0.004 0.008 d 11.80 12.00 12.20 0.464 0.472 0.480 d1 9.80 10.00 10.20 0.386 0.394 0.401 d3 8.00 0.315 e 11.80 12.00 12.20 0.464 0.472 0.480 e1 9.80 10.00 10.20 0.386 0.394 0.401 e3 8.00 0.315 e0.80 0.031 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 k 0?(min.), 3.5?(typ.), 7?(max.) ccc 0.10 0.0039 lqfp44 (10 x 10 x 1.4mm) 0076922 e
stlc3075 revision history 35/36 10 revision history table 18. document revision history date revision changes 04-oct-2004 1 initial release 04-nov-2004 2 removed all max. values of the ?line voltage? parameter on page 16/26. changed the unit from ma to% of the ?ilima? parameter on page 16/26. 09-feb-2005 3 added pin 4 pd in applications and block diagram. added table 2 ?esd rating?. 22-apr-2005 4 changed figures 9 and 10. 14-jul-2005 5 changed vttx value. 07-feb-2007 6 added rrx resistance in the figure 9 and figure 10 . updated section 4.1 and section 4.2.4 . updated r sense value and ipk maximum value in ta bl e 1 5 . updated figure 22 . added coilcraft references (fa2469-al and fa2470-al) to t1 parameter in ta b l e 1 2 . moved ta bl e 3 , ta bl e 4 and ta b l e 5 to chapter 9: package information . 09-mar-2007 7 added precision on single supply voltage range for fly-back and buck boost configurations on page 1. 10-mar-2009 8 document reformatted. updated section 9: package information on page 34
stlc3075 36/36 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of STLC307509

	To Download STLC307509 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .